The invention relates to fail processors.
It is known to generate patterns which are used in automatic test equipment by providing a high speed pattern generator which generates address sequences which are sent to a plurality of local generator circuits. Each local generator circuit includes a high speed local memory, a multiplicity of timing generators, a multiplicity of corresponding interpolators, a high speed formatter and a high speed fail processor. The timing generators and interpolators run in an interleaved fashion, with one timing generator/interpolator set receiving and generating all even cycle information and the other set receiving and generating all odd information.